A Coprocessor for Traffic Scheduling and Schedulability Analysis in FTT-CAN

The low-processing power microcontrollers used within typical CAN nodes, usually place tight limits on the complexity and flexibility of on-line message scheduling systems. One solution to break this barrier is to transfer the scheduling task to a hardware implementation. A traffic scheduling and schedulability analyser coprocessor is presented in this paper. The coprocessor generates message schedules for the master node CPU of a fieldbus system, leaving it just with the dispatching task. Scheduling can be made to follow one of three different policies. The number of messages to be scheduled and their parameters can be changed dynamically. To support on-line admission control of new messages, the coprocessor implements a schedulability analyser function. The coprocessor was designed to support the FTT-CAN protocol, but it can be adapted to any other fieldbus using centralised scheduling. The description presented here is focused mainly on the coprocessor’s overall functionality and interface with the node CPU. To characterise its performance, calculated response times are presented.